(SAR) ADC WITH CAPACITOR CHARGE DISTRIBUTION SELECTOR

Abstract

This work presents the design and implementation of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) architecture featuring a capacitor charge distribution selector. The proposed system enhances the traditional SAR ADC by incorporating multiplexers (CD4052B, CD4053B) and digital shift registers (74HC595) to dynamically manage the distribution of charge across the capacitor array during the conversion process. In a series capacitor connection the voltages are divided by equal pieces . With the help of a control circuit by selecting voltage level, we can complete a binary search Algorithm. A high-speed switching mechanism utilizing MOSFETs ensures minimal latency and improved accuracy in charge redistribution, which is critical for achieving high-resolution conversion. The design employs standard TTL logic gates (74LS series) for precise control logic and clock generation. The proposed architecture offers significant advantages in scalability, noise resilience, and power efficiency, making it well-suited for high-speed, low-power applications requiring moderate to high resolution. Simulation results validate the effectiveness of the charge distribution selector in optimizing the linearity and dynamic performance of the SAR ADC.