FPGA Based CNN Accelerator for Digit Recognition

Abstract

Digit recognition has become a critical application within the field of artificial intelligence, particularly for automation and embedded systems. While Convolutional Neural Networks (CNNs) are currently the standard for achieving high accuracy in these tasks, their implementation in traditional software environments often results in significant processing bottlenecks and high power consumption. This becomes a major limitation for modern applications that require real-time processing capabilities and high efficiency. This thesis focuses on the acceleration of a CNN system for handwritten digit recognition using the MNIST dataset through FPGA technology. The study follows a software-hardware co-design approach where the CNN architecture—incorporating convolution, ReLU activation, max-pooling, and fully connected layers—is first validated in software to ensure recognition performance. To overcome the sequential processing limitations of general-purpose CPUs, a hardware-based architecture is proposed. This design emphasizes the use of parallel processing units and pipelined dataflows to enhance speed. Furthermore, the implementation utilizes fixed-point representation to reduce the hardware resource requirements and complexity typically associated with floating-point operations. By leveraging the reconfigurable nature of FPGAs, the proposed system allows for the simultaneous execution of Multiply-Accumulate (MAC) operations. The analysis indicates that utilizing 8-bit fixed-point arithmetic allows for a significant reduction in hardware complexity while maintaining sufficient accuracy for the recognition task. Ultimately, this research demonstrates that FPGA-based acceleration provides a more efficient and faster alternative to traditional software implementations, making it suitable for deployment in real-time embedded environments.