End-to-End RTL to GDSII Design and Verification of SAP Processor Architectures

Abstract

The main objective of this project is to design and verify SAP processor architectures through a complete RTL-to-GDSII design flow. This work demonstrates how a digital processor can be implemented starting from a high-level hardware description down to a physical layout ready for fabrication. The SAP processor was developed using Verilog HDL, and its functionality was validated using comprehensive simulations and testbench verification. After confirming the design’s correctness, the RTL was synthesized and transformed into a GDSII layout, highlighting the challenges of timing, area optimization, and functional accuracy in physical design. This project provides practical exposure to processor design, hardware verification, and VLSI physical implementation, and serves as a foundation for further research on advanced processor architectures. The results show that the proposed methodology is effective for producing a reliable and verifiable processor design.